Performance Metrics & Analysis

Comprehensive performance analysis of the MHX™ Ternary RISC-V Core.

Overview

Neural Speedup

3x

vs software baseline

Optimized

Memory Savings

93.8%

Ternary encoding

Power Reduction

70%

Estimated savings

Efficiency Score

125.5

Combined metric

Performance Benchmarks

Computational Performance

Operation Software Hardware Speedup
16-trit Addition 48 cycles 1 cycle 48.0x
16-trit Multiplication 156 cycles 3 cycles 52.0x
Neural MAC 200 cycles 4 cycles 50.0x
Matrix Multiplication (4×4) 3,200 cycles 2,000 cycles 2.13x
TNN Inference (small network) 8,500 cycles 5,700 cycles 3x

Hardware Metrics

Area Breakdown

Component Area

Ternary ALU (2,500 gates) 16.7%
Ternary Register File (4,000 gates) 26.7%
Neural Unit (8,000 gates) 53.3%

Total MHX™ Overhead: 15,000 gates
Base Ibex Core: ~38,000 gates
Total with MHX™: ~53,000 gates

Relative Overhead

Base Ibex

100%

MHX™ Extensions

+40%

Power Consumption

Configuration Power (mW) Frequency Notes
Base Ibex (idle) 2.8 50 MHz 1.8V, no activity
MHX™ with extensions (idle) 3.2 50 MHz 1.8V, no activity
MHX™ full load 5 50 MHz 1.8V, all units active
Software emulation (baseline) 16.7 50 MHz Emulating ternary in software

Energy Efficiency

For equivalent ternary neural network workloads, the MHX™ extensions provide up to 70% power reduction compared to software emulation, while delivering 3x faster inference.

Timing Analysis

Metric Value Notes
Target Frequency 50 MHz Sky130 PDK
Critical Path ternary_multiply Ternary ALU multiply operation
Setup Slack 2 ns Positive slack, timing met
Hold Slack 0.5 ns All paths meet hold requirements

Memory Efficiency

Ternary encoding provides significant memory savings by representing ternary values natively instead of using full 32-bit integers.

Binary Representation

Value range: -1, 0, +1
Bits per value: 32 bits
16 values: 512 bits

Ternary Encoding

Value range: -1, 0, +1
Bits per value: 2 bits
16 values: 32 bits

Savings: 93.8%