About the Project

The MHX™ Ternary RISC-V Core extends the lowRISC Ibex processor with native support for ternary (base-3) computing and hardware-accelerated neural network operations. This extension enables efficient processing of ternary neural networks (TNNs) directly in hardware, providing significant performance and energy efficiency improvements for edge AI applications.

Key Features

• 32 Ternary Registers (T0-T31): Each holding 16 trits (32 bits total, 2 bits per trit)
• Ternary ALU: 15 native operations including arithmetic (ADD, SUB, MUL), logic (AND, OR, XOR, NOT), and advanced operations (dot product, distance metrics, reductions)
• Neural Processing Unit: 3-stage pipelined architecture with 16-entry weight cache, 4 activation functions (Sign, ReLU, Sigmoid, Tanh), hardware dropout, and batch normalization
• Dual Register File: 32 binary registers (x0-x31) + 32 ternary registers (t0-t31)
• Full Pipeline Integration: Seamless integration with standard RISC-V pipeline
• Formal Verification: Comprehensive formal proofs for all ternary operations with 20+ assertions
• Sparse Optimization: Skip-zero multiplication for 60% power reduction
• Weight Caching: 70% memory bandwidth reduction through LRU-managed cache

Performance Highlights

Documentation Sections

Section	Description
Quick Start	Get the core running in simulation
Architecture	Detailed architectural documentation
Instruction Set	Complete ISA reference
Integration Guide	How to integrate into your SoC
Security Analysis	Security considerations and mitigations
Verification	Test results and coverage reports