Instruction Set Reference

Complete reference for MHX™ ternary and neural extension instructions.

Custom Extension

These instructions use RISC-V custom opcode space (custom-0 and custom-1) and are not part of the standard RISC-V ISA.

Ternary Register File

The MHX™ extension adds 16 ternary registers (t0-t15), each holding 16 trits (ternary digits). Each trit can hold values -1, 0, or +1.

Register ABI Name Description
t0 tzero Hardwired to zero (16 trits of 0)
t1-t7 ta0-ta6 Argument/return registers
t8-t11 ts0-ts3 Saved registers
t12-t15 tt0-tt3 Temporary registers

Ternary ALU Instructions

Basic ternary arithmetic and logical operations. All operations work on 16-trit values with proper overflow/underflow handling.

Mnemonic Operands Description Opcode
t.add td, ts1, ts2 Ternary addition with overflow detection 0x0B / 0x00
t.sub td, ts1, ts2 Ternary subtraction with borrow handling 0x0B / 0x01
t.mul td, ts1, ts2 Ternary multiplication (16-trit) 0x0B / 0x02
t.and td, ts1, ts2 Ternary logical AND (min operation) 0x0B / 0x03
t.or td, ts1, ts2 Ternary logical OR (max operation) 0x0B / 0x04
t.xor td, ts1, ts2 Ternary logical XOR 0x0B / 0x05
t.not td, ts1 Ternary logical NOT (negation) 0x0B / 0x06

Instruction Details

t.add - Ternary Addition

t.add td, ts1, ts2    # td = ts1 + ts2

Performs trit-by-trit addition with carry propagation. Each trit result is clamped to the range [-1, +1] with overflow detection. The overflow flag is set in the CSR if the result exceeds representable range.

# Addition truth table for single trit:

-1 + -1 = -1 (overflow)

-1 + 0 = -1

-1 + +1 = 0

0 + 0 = 0

0 + +1 = +1

+1 + +1 = +1 (overflow)

t.mul - Ternary Multiplication

t.mul td, ts1, ts2    # td = ts1 * ts2

Performs ternary multiplication. For single trits, this follows the simple rule:

  • -1 × -1 = +1
  • -1 × 0 = 0
  • -1 × +1 = -1
  • 0 × anything = 0
  • +1 × +1 = +1

Neural Unit Instructions

Hardware-accelerated neural network operations optimized for ternary neural networks (TNNs).

Mnemonic Operands Description Opcode
n.mac td, ts1, ts2, ts3 Multiply-accumulate: td = ts1 * ts2 + ts3 0x2B / 0x00
n.relu td, ts1 ReLU activation: td = max(0, ts1) 0x2B / 0x01
n.sigmoid td, ts1 Sigmoid activation (LUT-based) 0x2B / 0x02
n.tanh td, ts1 Tanh activation (LUT-based) 0x2B / 0x03
n.bias td, ts1, imm Add bias: td = ts1 + imm 0x2B / 0x04

Instruction Details

n.mac - Multiply-Accumulate

n.mac td, ts1, ts2, ts3    # td = ts1 * ts2 + ts3

The core neural network operation. Performs a fused multiply-accumulate in a single cycle, essential for efficient matrix operations and convolutions.

n.relu - ReLU Activation

n.relu td, ts1    # td = max(0, ts1)

Applies the Rectified Linear Unit activation function. For ternary values, this maps:

  • -1 → 0
  • 0 → 0
  • +1 → +1

Encoding Format

MHX™ instructions use the RISC-V R-type encoding format in the custom opcode space: 

31       25 24   20 19   15 14  12 11    7 6      0
┌──────────┬───────┬───────┬──────┬───────┬────────┐
│  funct7  │  rs2  │  rs1  │funct3│   rd  │ opcode │
│  7 bits  │5 bits │5 bits │3 bits│5 bits │ 7 bits │
└──────────┴───────┴───────┴──────┴───────┴────────┘

Ternary ALU: opcode = 0x0B (custom-0)
Neural Unit: opcode = 0x2B (custom-1)

Example Code

# Simple ternary neural network layer
# Input: t1, Weights: t2, Bias: t3
# Output: t4

# Multiply-accumulate
n.mac   t4, t1, t2, t3    # t4 = t1 * t2 + t3

# Apply ReLU activation
n.relu  t4, t4            # t4 = max(0, t4)

# Store result
t.mv    t5, t4            # Copy to output register