Integration Guide

How to integrate the MHX™ Ternary RISC-V Core into your System-on-Chip design.

Overview

The MHX™ Ternary Ibex core is designed as a drop-in replacement for the standard Ibex core, with additional interfaces for ternary memory access and neural unit configuration.

Top-Level Interface

The core exposes the following key interfaces:

Standard Ibex Interfaces

• Instruction memory interface - Standard 32-bit instruction fetch
• Data memory interface - Standard 32-bit data load/store
• Interrupt interface - External, timer, and software interrupts
• Debug interface - RISC-V debug specification compliant

MHX™ Extension Interfaces

module ibex_core #(
  // Standard Ibex parameters
  parameter bit          PMPEnable        = 1'b0,
  parameter int unsigned PMPGranularity   = 0,
  parameter int unsigned PMPNumRegions    = 4,
  // ... other standard params
  
  // MHX™ Extension parameters
  parameter bit          TernarySupport   = 1'b1,
  parameter bit          NeuralSupport    = 1'b1,
  parameter int unsigned TernaryRegCount  = 16,
  parameter int unsigned NeuralMacUnits   = 4
) (
  // Standard interfaces
  input  logic        clk_i,
  input  logic        rst_ni,
  
  // Instruction memory interface
  output logic        instr_req_o,
  input  logic        instr_gnt_i,
  // ...
  
  // Data memory interface
  output logic        data_req_o,
  input  logic        data_gnt_i,
  // ...
  
  // MHX™ Ternary memory interface (optional)
  output logic        ternary_mem_req_o,
  output logic [31:0] ternary_mem_addr_o,
  output logic [31:0] ternary_mem_wdata_o,
  input  logic [31:0] ternary_mem_rdata_i,
  input  logic        ternary_mem_gnt_i,
  
  // Neural unit configuration
  input  logic [7:0]  neural_config_i,
  output logic        neural_busy_o
);

Configuration Parameters

Memory Map

The ternary extension uses memory-mapped CSRs for configuration and status:

0x7C0 - TERNARY_STATUS  : Ternary unit status register
0x7C1 - TERNARY_CTRL    : Ternary unit control register
0x7C2 - NEURAL_STATUS   : Neural unit status register
0x7C3 - NEURAL_CTRL     : Neural unit control register
0x7C4 - NEURAL_CONFIG   : Neural unit configuration

Integration Steps

1. Add Source Files

Include the following RTL files in your build:

rtl/ibex_ternary_alu.sv
rtl/ibex_ternary_regfile.sv
rtl/ibex_neural_unit.sv
rtl/ibex_pkg.sv (modified)
rtl/ibex_decoder.sv (modified)
rtl/ibex_core.sv (modified)

2. Connect Interfaces

ibex_core #(
  .TernarySupport(1'b1),
  .NeuralSupport(1'b1)
) u_ibex_core (
  .clk_i(clk),
  .rst_ni(rst_n),
  
  // Standard connections
  .instr_req_o(instr_req),
  .instr_gnt_i(instr_gnt),
  // ...
  
  // Optional: dedicated ternary memory
  .ternary_mem_req_o(ternary_mem_req),
  .ternary_mem_addr_o(ternary_mem_addr),
  // ...
);

3. Synthesis Constraints

For optimal timing, add the following constraints:

# Ternary ALU is the critical path
set_max_delay 5.0 -from [get_pins u_ibex_core/u_ternary_alu/*] \
                  -to [get_pins u_ibex_core/u_ternary_regfile/*]

# Neural MAC units can be pipelined
set_multicycle_path 2 -setup -from [get_pins u_ibex_core/u_neural_unit/mac_*]

Area and Timing Estimates

Verification Checklist

• ✅ Run fusesoc ... --TernarySupport=true lint checks
• ✅ Execute ternary unit tests
• ✅ Run formal verification on ternary ALU
• ✅ Verify neural unit with known test vectors
• ✅ Check timing with synthesis tools
• ✅ Validate power estimates