Security Analysis

Security considerations, threat model, and mitigations for the MHX™ Ternary RISC-V Core.

Security Notice

This core is currently in development and has NOT undergone formal security certification. Do not use in production security-critical applications without thorough review.

Threat Model

The MHX™ Ternary extension introduces new attack surfaces that must be considered in security-sensitive applications.

Asset Identification

  • Neural network weights - Proprietary trained models in ternary format
  • Inference data - Input data to neural network operations
  • Ternary register contents - May contain sensitive intermediate values
  • Execution integrity - Correct execution of ternary/neural operations

Potential Threats

HIGH

Timing Side Channels

Ternary multiplication timing may vary based on operand values, potentially leaking information about neural network weights.

MEDIUM

Power Analysis

Neural MAC operations have data-dependent power consumption that could reveal weights through DPA attacks.

MEDIUM

Fault Injection

Glitching attacks could corrupt ternary computations, leading to incorrect inference results with security implications.

LOW

Register Leakage

Ternary registers may retain sensitive values after context switches if not properly cleared.

Mitigations

Constant-Time Operations

The ternary ALU is designed with constant-time execution for all operations: 

// Constant-time ternary multiplication (simplified)
always_comb begin
  // All paths take same number of cycles regardless of operand values
  for (int i = 0; i < TRIT_WIDTH; i++) begin
    // Lookup table approach - constant time
    mult_result[i] = TRIT_MULT_TABLE[op_a[i]][op_b[i]];
  end
end

Register Clearing

Software should clear ternary registers before context switches: 

# Clear all ternary registers before context switch
t.li t1, 0
t.li t2, 0
# ... repeat for all registers
t.li t15, 0

Fault Detection

The neural unit includes optional redundancy checking:

  • Dual-rail encoding for critical operations
  • Result parity checking
  • Instruction sequence monitoring

Security CSRs

CSR Address Description
TSEC_CTRL 0x7D0 Ternary security control (enable constant-time mode)
TSEC_STATUS 0x7D1 Ternary security status (fault detected, etc.)
NSEC_CTRL 0x7D2 Neural unit security control

Recommendations

✅ Do

  • Enable constant-time mode for sensitive operations
  • Clear ternary registers on context switch
  • Use hardware fault detection when available
  • Implement proper access control to neural weights

❌ Don't

  • Store cryptographic keys in ternary registers
  • Use in safety-critical applications without review
  • Assume ternary operations are inherently secure
  • Ignore power/timing side channels in threat model

Future Work

  • Formal verification of constant-time properties
  • Hardware randomization of neural computations
  • Integration with Ibex lockstep mode
  • Side-channel resistant activation functions