MHX™ Ternary Extension

Ternary RISC-V Core

Extending the lowRISC Ibex core with native ternary computing support and hardware-accelerated neural processing capabilities.

Documentation View on GitHub

Project Overview

CI Status

Passing

Last run: 1/23/2026

Neural Speedup

vs baseline implementation

Optimized

Memory Reduction

93.75%

Ternary encoding efficiency

Efficiency Score

211.0

Overall performance index

Floorplan Architecture

The MHX™ Core integrates seamlessly into the Ibex pipeline with dedicated ternary processing units, neural acceleration hardware, and a dual register file architecture.

Core Pipeline (IF/ID/EX stages)

Ternary ALU (15 operations, 16-trit)

Neural Processing Unit (3-stage pipelined)

Dual Register File (32 binary + 32 ternary)

Weight Cache (16 entries, LRU)

View full architecture details

Verification Status

Test Suites

RTL Linting (Verilator)

Passing

~2min

RTL Linting (Verible)

Passing

~1min

Ternary ALU Tests

All operations verified

Passing

Neural Unit Tests

MAC, activation functions

Passing

Read/write integrity

Passing

Integration Tests

Full pipeline

Passing

Formal Verification

50+ assertions

Passing

Code Coverage

Line Coverage 85.2%

Branch Coverage 78.5%

Function Coverage 92.1%

Coverage by Module

ibex_ternary_alu.sv 95.0%

ibex_neural_unit.sv 88.0%

ibex_ternary_regfile.sv 92.0%

ibex_decoder.sv 82.0%

Performance Metrics

Neural Inference

Speedup vs software

Matrix Operations

2.13x

Speedup for matrix ops

Power Reduction

70%

Estimated power savings

Quick Links

Instruction Set

Complete ISA reference for ternary and neural instructions

Integration Guide

How to integrate the MHX™ core into your SoC

Security Analysis

Security considerations and threat model

Verification Reports

Test results, coverage, and formal proofs

View Detailed Performance Metrics